The first generation of optical fiber systems in the public telephone network used proprietary architectures, equipment line codes, multiplexing formats, and maintenance procedures. This diversity complicated the task of the regional Bell operating companies (“RBOCs”) and the interexchange carriers (e.g., AT&T, Sprint, MCI, etc.) who needed to interface their equipment with these diverse systems.
To ease this task, Bellcore initiated an effort to establish a standard for connecting one optical fiber system to another. That standard is officially named the Synchronous Optical Network, but it is more commonly called “SONET.” The international version of the domestic SONET standard is officially named the Synchronous Digital Hierarchy, but it is more commonly called “SDH.”
Although differences exist between SONET and SDH, those differences are mostly in terminology. In most respects, the two standards are the same and, therefore, virtually all equipment that complies with either the SONET standard or the SDH standard also complies with the other. Therefore, for the purposes of this specification, the SONET standard and the SDH standard shall be considered interchangeable and the acronym/initialism “SONET/SDH” is defined as either the Synchronous Optical Network standard or the Synchronous Digital Hierarchy standard or both.
The nodes in a SONET/SDH network are synchronized to each other. In particular, SONET/SDH is governed by both frame synchronization and network synchronization. In frame synchronization, a SONET/SDH signal carries its frame pattern within its bit stream. A SONET/SDH receiver must establish frame synchronization before it can restore the bit stream of the SONET/SDH signal. In network synchronization, information transfer between interconnected synchronous systems must be possible without the data buffers in the network overflowing or buffer underflowing. Otherwise, if a buffer overflows or underflows, the underlying timing mismatch introduces degradation into the information message signal.
Underlying synchronization at both the frame level and network level is the need to have adequate timing recovery in the digital transmission system, whether or not it is SONET/SDH based. Timing recovery at equipment receiving a digital bit stream includes two issues. The first issue is how to obtain the reference clock (i.e., timing information), and the second issue is how to synchronize this clock to a benchmark or standard phase. Techniques exist in the prior art that address timing recovery issues. Furthermore, techniques to provide timing information to multiple equipment nodes exist in the prior art, as discussed below.
FIG. 1 depicts a block diagram of telecommunications network 100 in the prior art, which comprises a SONET/SDH ring network operating as a bi-directional line switching ring (“BLSR”). Telecommunications network 100 comprises five central offices, central office 101, 102, 103, 104, and 105, in which each pair of adjacent central offices is interconnected by two high-speed digital transmission lines.
Central office 101, 102, 103, 104, and 105 are interconnected for timing purposes as well as for voice and data transmission purposes. Timing interconnection in a high-speed digital network, such as telecommunications network 100, is critical for the purposes of successfully interpreting and decoding the digital information exchanged between equipment nodes.
FIG. 2 depicts a block diagram of the salient components of central office 101 in the prior art. As shown in FIG. 2, equipment cabinet 201, 202, 203, and 204 represent different telecommunications equipment nodes within central office 101. Equipment cabinet 201 constitutes a SONET/SDH node. Equipment cabinet 201 in central office 101 communicates with other SONET/SDH nodes in interconnected central office 102 via fiber 111-2-1 and fiber 112-1-2, and in central office 104 via fiber 111-1-4 and 1124-1.
Equipment cabinet 202 and 203 are T-carrier terminations. T-carrier (e.g., T-1, T-3, etc.) is a system that is used for digital telecommunication transmission. Equipment cabinet 202 interconnects with a node external to central office 101 via a dedicated T-carrier link. Equipment cabinet 203 interconnects with a node external to central office 101 via another dedicated T-carrier link.
Equipment cabinet 204 serves as an internal timing source (i.e., internal clock) for equipment within central office 101. As an internal timing source, equipment cabinet 204 can bridge, with automatic switching, short disruptions of whatever timing source is being used are the primary source. The accuracy of the internal timing source is rated at a minimum acceptable level of performance (e.g., ±20 parts per million or better, etc.).
Timing distribution system 205 provides the major source of integrated timing information within central office 101. Timing distribution system 205 accepts designated sources of timing information, evaluates the timing information against performance criteria, derives a stabilized timing signal, and then makes the timing signal available to the equipment requiring timing information. In essence, timing distribution system 205 is a source node for timing information to other nodes that require timing information.
Timing distribution system 205 accepts timing signals from a variety of sources. Path 211-1 and path 211-2 receive timing information from clock recovery circuit 206-1 and 206-2, respectively. Clock recovery circuit 206-1 through 206-5, in general, recover timing information from the information message signal in which timing is embedded. This information message signal can be SONET/SDH, T-1, T-3, or other time-division-multiplexed service signals. In the case of clock recovery circuit 206-1 and 206-2, the timing information originates from central office 102 via fiber 111-2-1 and from central office 104 via fiber 112-4-1, respectively, and is embedded within the SONET/SDH signal received. Similarly, path 211-3 provides timing information to timing distribution system 205 from SONET/SDH tributary 121. Clock recovery circuit 206-3 extracts the timing information.
Other sources of timing terminate into timing distribution system 205. Path 211-4 and 211-5 provide timing information recovered from the T-carrier links via clock recovery circuit 2064 and 206-5, respectively.
Timing distribution system 205 also accepts timing signals directly from external timing sources. Path 211-6 and 211-7 carry timing information known as BITS, or Building Integrated Timing Supply, widely used in digital networks. BITS allows for a standardized timing supply for digital networks. BITS_IN interface 207-1 and 207-2 terminate BITS signs on paths 117 and 118, respectively, and provides the BITS signals to path 211-6 and 211-7.
In addition to a variety of other possible timing inputs that are not depicted, path 211-N provides timing distribution system 205 with the timing signal from the internal clock constituting equipment cabinet 204. The number N refers to the total number of input timing information paths to timing distribution system 205.
Timing distribution system 205 also serves as a timing source node by providing timing information to receiver nodes requiring timing for synchronization purposes. Path 212-1 provides timing information to equipment cabinet 201, the SONET/SDH node within central office 101. Path 212-2 provides timing information to equipment cabinet 203, a T-carrier node. Path 212-3 provides timing information to BITS_OUT interface 208, which, in turn, provides the timing signal to a timing receiver node at a location external to central office 101 via path 119.
Other paths can provide timing information to various nodes within central office 101, external to central office 101, or both. One such path is path 212-M, which provides timing information to equipment cabinet 202, a T-carrier node. The number of output timing paths, M, can be less than, greater than, or equal to the number of input timing paths, N.
FIG. 3 depicts a block diagram of timing distribution system 205 in the prior art. Timing distribution system 205 comprises a single timing processing path. As depicted in FIG. 3, the timing processing path comprises evaluator/selector 302 and timing signal generator 303. Evaluator/selector 302 accepts a plurality of candidate timing signals 211-1 through 211-(N−1). Evaluator/selector 302 also accepts a benchmark signal (i.e., from the internal timing source depicted in FIG. 2) on path 211-N. Evaluator/selector 302 is depicted in FIG. 4 and will be discussed later in more detail.
Evaluator/selector 302 evaluates the candidate signals and selects a single active timing signal, providing it to timing signal generator 303 via path 311. Timing signal generator 303 takes the timing signal and derives a stabilized signal by passing the timing signal through a phase locked loop. Timing signal generator 303 then provides the stabilized timing signal to the receiver nodes via paths 212-1 through 212-M.
Timing signal generator 303 also accepts a backup timing signal (i.e., from the internal timing source depicted in FIG. 2) via path 211-N. The backup signal is also stabilized through the phase locked loop and is used for holdover purposes, in the event that the primary timing signal is interrupted.
FIG. 4 depicts a block diagram of evaluator/selector 302. Evaluator/selector 302 accepts a plurality of candidate signals via paths 211-1 through 211-(N−1). Evaluator 401-h, for h=1 to (N−1), accepts the candidate signal transmitted on path 211-h, appraises a characteristic of the candidate signal against that of the benchmark signal provided via path 211-N, and compares the difference to a threshold. Evaluator 401-h then provides an evaluation signal to controller 402 via path 411-h, wherein the evaluation signal is an indication of the outcome of the evaluation.
Controller 402 is used to process evaluation signals on path 411-h, for h=1 to (N−1). Controller 402 accepts the evaluation signals and derives a selection signal, provided to (N−1)-to-1 selector 403 via path 412. The selection signal can be derived by controller 402 in part by examining the evaluation signals, it is can be derived through other means.
Selector 403 accepts the selection signal via path 412 and uses the selection signal to select the candidate signal from path 211-1 through 211-(N−1) that is to be provided as output from evaluator/selector 302 via path 311.
As discussed, techniques exist in the prior art that address timing recovery and distribution. However, many of these techniques are limited in providing the flexibility that telecommunications operators require in various operating environments, in particular where there are numerous equipment nodes requiring timing information. A technique is needed that that would provide operators with the timing recovery and distribution flexibility that they require, especially as synchronized telecommunications networks grow larger and more complex.